1. Field of the Invention
This invention relates generally to integrated circuits (ICs) and, more particularly, to bipolar transistors with vertical structures.
2. Discussion of the Related Art
Modern compound semiconductor bipolar transistors have vertical structures. In these structures, reducing the base parasitic resistance (RBB) and the base-collector capacitance (CBC) are important for achieving a higher maximum frequency of oscillation (fmax), because fmax≈(fτ/[8πRBBCBC)1/2, where fτ is the cutoff frequency. Reducing RBB and CBC increases fmax and thus, improves transistor performance. In addition, fτ will also increase as CBC decreases, since ½πfτ=τb+τc+kT/qIc (CJE+CBC)+(REE+RCC)CBC. Where τb and τc are the base and collector transit times, CJE is the emitter junction capacitance, REE and RCC are the extrinsic emitter and collector resistances, k is the Boltzmann constant, T is the absolute temperature, q is the electron charge, and Ic is the collector current.
FIG. 1 shows a mesa vertical structure 10 for a conventional bipolar transistor. The mesa vertical structure 10 is located on a substrate 8 with a high resistance, e.g., iron (Fe) doped indium phosphide (InP). The mesa vertical structure 10 includes collector, base, and emitter layers 14, 16, 18 and collector, base, and emitter electrodes 20, 22, 24. The mesa vertical structure 10 also includes a subcollector contact layer 19. The subcollector contact layer 19 is heavily doped to provide a conducting electrical connection between the collector layer 14 and the collector metal electrode 20.
The base's metal electrode 22 is self-aligned to the emitter metal electrode 24 to reduce the base parasitic resistance. In particular, edge surfaces 26, 28 of the metal electrodes 24, 22 are aligned in the lateral direction, L. Here, L is directed along the surface of the layers 16. The lateral alignment of the emitter and base electrodes 24, 22 minimizes the length of the current pathway in the portion 30 of the base layer 16, which is located in the transistor's extrinsic region 12. Minimizing the length of this current pathway lowers the associated resistance and thus, reduces the base parasitic resistance.
While laterally aligning the edges 26, 28 of the base and emitter electrodes 22, 24 does reduce the base parasitic resistance, the parasitic resistance still increases as device dimensions are vertically scaled down. In particular, thinning the base layer 16 increases the sheet resistance therein. The higher sheet resistance will, in turn, produce a higher base parasitic resistance. Although, thinning the base layer 16 may slightly increase the base-collector capacitance, CBC, there is a greater advantage in the reduction of τb to increase both fmax and fτ. Both a higher base parasitic resistance and a higher base-collector capacitance will reduce the maximum frequency of oscillation, i.e., fmax, of the bipolar transistor. Consequently, even the laterally aligned structure 10 will not produce acceptably low base parasitic resistances and base-collector capacitances as the thickness of the base layer 16 is scaled down.
Plans to scale down feature dimensions in bipolar transistors often include scaling down the thickness of the emitter layer 18 to further reduce the transit time, ft. The emitter layer 18 provides vertical electrical isolation between the base and emitter electrodes 22, 24 in the structure 10. In particular, a vertical gap separates these metal contacts 22, 24, and the gap has a width that is equal to the excess thickness, d, of the emitter layer 18 over the thickness of the base electrode 22. As the thickness of the emitter layer 18 scales down, this excess thickness, d, will become insufficient to provide electrical isolation between the base and emitter electrodes 22, 24.
Finally, bipolar transistors are often incorporated into ICs where many devices are fabricated on a substrate and then covered by dielectric and metal interconnect layers. In an IC, a planar device structure is better than a mesa structure for process integration. In particular, via, device and interconnect dimensions can be scaled down for planar structures. Also, lithography is easier, since step heights are smaller in planar structures. A more planar transistor structure also provides better heat dissipation than a mesa structure, because the surrounding regions have a better thermal conductivity if they are a semiconductor, such as InP, rather that a dielectric. The planar structure is desirable for large-scale process integration and device scaling.
As the desire for improved performance pushes for bipolar transistors with yet thinner base and/or emitter layers and yet smaller lateral dimensions, the smaller device dimensions will further exacerbate the above-described problems for the mesa vertical structure 10 of FIG. 1.